The present invention relates to a manufacturing technology of a semiconductor device and the semiconductor device, for example, a technology effective when applied to a semiconductor device obtained by mounting a semiconductor chip on a wiring substrate via a bump electrode.
Japanese Patent Laid-Open No. 2008-80396 (Patent Document 1) describes a solder paste composition to be used for precoating the surface of an electrode with a solder and containing a solder powder or a precipitation type solder material and a flux.
Japanese Patent Laid-Open No. Hei 5(1993)-308184 (Patent Document 2) describes a solder-coated circuit board having, on a pad thereof, a solder layer having a thickness necessary for soldering a component lead. The pad has such a structure that it has a width partially increased in a pad length direction and has, on the resulting wide-width portion, a solder bump portion having a solder layer thicker than that of another portion.
WO2009/034628 (Patent Document 3) describes a solder precoated substrate having a coupling conductor pattern comprised of a wiring pattern which will be a wiring and a coupling pad formed continuously with the wiring pattern at a position at which a bump provided on an electronic part is to be bonded. The coupling pad is formed so as to have a width size greater than that of the wiring pattern.
Japanese Patent Laid-Open No. 2000-77471 (Patent Document 4) describes a flip chip packaging substrate having a conductor pattern comprised of a wiring pattern and a coupling pad to which a bump is to be bonded. Further, it describes a technology of forming the coupling pad so as to have a width size greater than that of the wiring pattern.
[Patent Document 1] Japanese Patent Laid-Open No. 2008-80396
[Patent Document 2] Japanese Patent Laid-Open No. Hei 5(1993)-308184
[Patent Document 3] WO2009/034628
[Patent Document 4] Japanese Patent Laid-Open No. 2000-77471